When packet A was writing to memory, packet B arrived.
A's tail was replaced by B's head.
B lost his head.
A and B were silently and wrongly wrote.

If memory is shared by ethmac and other busy masters,
ethmac occasionally can't finish the writing of A before
next packet B coming in. At this state, I think A should
be abort, mark A as overrun, and keep B as one piece.

I heard some one said, ethmac has some problems on heavily load,
maybe this is the reason.

I reconfigured the testbench, intend to trigger the problem.

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cd scripts
gmake cop_rtl-tests VCD=1
gtkwave ../build/sim/ethmac.vcd wishbone_bus.sav
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Pay attention to "wb_dat_i" @14885ns. FIFO be resetted while writing is not finished yet.

I can not find out an easy way (just change several lines) to fix the problem.

It seems the assumption (A can write all bytes back to memory before B comes) is an
very essential assumption crossed whole eth_wishbone.v .

Have to reconstruct eth_wishbone.v to wipe out the problem ?

Any comment ?

BTW. Eth_wishbone.v is not very efficiency on burst. You can see it in vcd.